1. Field of the Invention
The present invention relates to an overcurrent protection circuit for a voltage regulator.
2. Description of the Related Art
A conventional voltage regulator is described. FIG. 3 is a circuit diagram illustrating the conventional voltage regulator.
The conventional voltage regulator includes a reference voltage circuit 101, a differential amplifier circuit 102, a PMOS transistor 105 serving as an output transistor, an overcurrent protection circuit 361, resistors 107 and 108, a ground terminal 100, an output terminal 121, and a power supply terminal 150. The overcurrent protection circuit 361 includes NMOS transistors 132, 133, and 138, a PMOS transistor 131 serving as a sense transistor, and PMOS transistors 134, 135, 136, and 137.
The differential amplifier circuit 102 has an inverting input terminal connected to the reference voltage circuit 101 and a non-inverting input terminal connected to a connection point between the resistors 107 and 108. The PMOS transistor 131 has a gate connected to an output terminal of the differential amplifier circuit 102 and a source connected to the power supply terminal 150. The NMOS transistor 132 has a gate and a drain which are connected to a drain of the PMOS transistor 131, and a source connected to the ground terminal 100. The NMOS transistor 133 has a gate connected to the gate of the NMOS transistor 132 and a source connected to the ground terminal 100. The PMOS transistor 134 has a source connected to the power supply terminal 150 and a gate and a drain which are connected to a drain of the NMOS transistor 133.
The PMOS transistor 135 has a gate connected to the gate of the PMOS transistor 134, a drain connected to the output terminal of the differential amplifier circuit 102, and a source connected to the power supply terminal 150. The NMOS transistor 138 has a gate connected to the gate of the NMOS transistor 132 and a source connected to the output terminal 121. The PMOS transistor 136 has a gate and a drain which are connected to a drain of the NMOS transistor 138, and a source connected to the power supply terminal 150. The PMOS transistor 137 has a gate connected to the gate of the PMOS transistor 136, a drain connected to the output terminal of the differential amplifier circuit 102, and a source connected to the power supply terminal 150. The PMOS transistor 105 has a gate connected to the output terminal of the differential amplifier circuit 102, a source connected to the power supply terminal 150, and a drain connected to the output terminal 121.
The resistor 107 and the resistor 108 are connected between the output terminal 121 and the ground terminal 100 (see, for example, Japanese Patent Application Laid-open No. 2010-218543).
The conventional voltage regulator operates as follows to protect the circuit from an overcurrent. If the output terminal and the ground terminal of the voltage regulator are short-circuited, an output current Iout increases. When the output current Iout increases, a current flowing through the sense transistor 131 also increases, and a current flowing through the NMOS transistor 132 also increases. A current flowing through the NMOS transistor 133, which is current-mirror-connected to the NMOS transistor 132, also increases, and a current flowing through the PMOS transistor 134 also increases. The ON-state resistance of the PMOS transistor 135, which is current-mirror-connected to the PMOS transistor 134, decreases, and a gate-source voltage of the output transistor 105 decreases so that the output transistor 105 is gradually turned OFF. Accordingly, the output current Iout reduces, and an output voltage Vout decreases.
When the output voltage Vout decreases to be equal to or lower than a predetermined voltage, a gate-source voltage of the NMOS transistor 138 becomes equal to or higher than a threshold voltage, and the NMOS transistor 138 is turned ON. Then, a current flowing through the PMOS transistor 136 increases, and the ON-state resistance of the PMOS transistor 137, which is current-mirror-connected to the PMOS transistor 136, decreases. The gate-source voltage of the output transistor 105 further decreases, and the output transistor 105 is further turned OFF. Accordingly, the output current Iout further reduces and becomes a short-circuit output current Is. After that, the output voltage Vout further decreases to be 0 volts.
In the conventional technology, however, when an input/output voltage difference is small, the overcurrent protection is not enabled unless the output voltage reduces to a certain level, and hence there has been a problem in that a connected IC is broken by an overcurrent. Further, the amount of reduction of the output voltage cannot be controlled, and hence there has been another problem in that a good fold-back characteristic is difficult to obtain.